#include <stdio.h>
#include "csg_sdk_hal.h"
#include "csg_sdk_soc.h"

#include "los_base.h"
#include "los_typedef.h"
#include "los_tick.h"

#include "mem.h"
#include "main.h"
#include "osal.h"

#include "los_swtmr.h"
#include "csg_libopt.h"

#include "ff.h"
#include "diskio.h"
#include "pcram.h"
#include "csg_rtc.h"

#if defined (__CC_ARM)
extern char __heap_start__ [];
#elif defined (__GNUC__)
extern char __los_heap_addr_start__ [];
extern char __los_heap_addr_end__ [];
#else
#error "fix me"
#endif

const struct phys_mem system_phys_mem [] =
    {
#if defined (__CC_ARM)
        { __heap_start__, (char *) 0x2002FC00, },
#elif defined (__GNUC__)
        {(unsigned long)__los_heap_addr_start__, (unsigned long)__los_heap_addr_end__, },
#else
#error "fix me"
#endif
        { 0, 0 }
    };
/////////////////////////////////////////////////////FatFS
FATFS fs_flash;			/* FatFS object*/
FATFS fs_pcram;			/* FatFS object*/
FIL fnew;			/* File object */
FIL fp;
FRESULT res_pcram_a;              /*File result*/
scFRESULT res_flash;
scFRESULT res_pcram_b;
UINT fnum;  
BYTE ReadBuffer[4096]={0};        /* File read buffer */
BYTE WriteBuffer[4096] =             /* File write buffer */
"abcdef0123456789";
//   "This is a demo in scfat area as regular file 0050,This is a demo in scfat area as regular file 0100,This is a demo in scfat area as regular f 0150,This is a demo in scfat area as regular file 0200,This is a demo in scfat area as regular file 0250,This is a demo in scfat area as regular file 0300,This is a demo in scfat area as regular file 0350,This is a demo in scfat area as regular file 0400,This is a demo in scfat area as regular file 0450,This is a demo in scfat area as regular file 0500,\
//   This is 0512\
//   XX in scfat area as regular file 0550,This is a demo in scfat area as regular file 0600,This is a demo in scfat area as regular f 0650,This is a demo in scfat area as regular file 0700,This is a demo in scfat area as regular file 0750,This is a demo in scfat area as regular file 0800,This is a demo in scfat area as regular file 0850,This is a demo in scfat area as regular file 0900,This is a demo in scfat area as regular file 0950,This is a demo in scfat area as regular file 1000,\
//   these words count 1024!!\
//   This is a demo in scfat area as regular file 0050,This is a demo in scfat area as regular file 0100,This is a demo in scfat area as regular f 0150,This is a demo in scfat area as regular file 0200,This is a demo in scfat area as regular file 0250,This is a demo in scfat area as regular file 0300,This is a demo in scfat area as regular file 0350,This is a demo in scfat area as regular file 0400,This is a demo in scfat area as regular file 0450,This is a demo in scfat area as regular file 0500,\
//   This is 1536XX in scfat area as regular file 0550,This is a demo in scfat area as regular file 0600,This is a demo in scfat area as regular f 0650,This is a demo in scfat area as regular file 0700,This is a demo in scfat area as regular file 0750,This is a demo in scfat area as regular file 0800,This is a demo in scfat area as regular file 0850,This is a demo in scfat area as regular file 0900,This is a demo in scfat area as regular file 0950,This is a demo in scfat area as regular file 1000,\
//   these words count 2048!!\
//   This is a demo in scfat area as regular file 0050,This is a demo in scfat area as regular file 0100,This is a demo in scfat area as regular f 0150,This is a demo in scfat area as regular file 0200,This is a demo in scfat area as regular file 0250,This is a demo in scfat area as regular file 0300,This is a demo in scfat area as regular file 0350,This is a demo in scfat area as regular file 0400,This is a demo in scfat area as regular file 0450,This is a demo in scfat area as regular file 0500,\
//   This is 2560XX in scfat area as regular file 0550,This is a demo in scfat area as regular file 0600,This is a demo in scfat area as regular f 0650,This is a demo in scfat area as regular file 0700,This is a demo in scfat area as regular file 0750,This is a demo in scfat area as regular file 0800,This is a demo in scfat area as regular file 0850,This is a demo in scfat area as regular file 0900,This is a demo in scfat area as regular file 0950,This is a demo in scfat area as regular file 1000,\
//   these words count 3072!!\
//   This is a demo in scfat area as regular file 0050,This is a demo in scfat area as regular file 0100,This is a demo in scfat area as regular f 0150,This is a demo in scfat area as regular file 0200,This is a demo in scfat area as regular file 0250,This is a demo in scfat area as regular file 0300,This is a demo in scfat area as regular file 0350,This is a demo in scfat area as regular file 0400,This is a demo in scfat area as regular file 0450,This is a demo in scfat area as regular file 0500,\
//   This is 3584XX in scfat area as regular file 0550,This is a demo in scfat area as regular file 0600,This is a demo in scfat area as regular f 0650,This is a demo in scfat area as regular file 0700,This is a demo in scfat area as regular file 0750,This is a demo in scfat area as regular file 0800,This is a demo in scfat area as regular file 0850,This is a demo in scfat area as regular file 0900,This is a demo in scfat area as regular file 0950,This is a demo in scfat area as regular file 1000,\
//   these words count 4096!";
int gong_hao_write_repeat_num = 1;
int gong_hao_read_repeat_num = 1;
int DEFAULT_DELAY_CNT = 100;
/////////////////////////////////////////////////////FatFS
/////////////////////////////////////////////////////GMC test
uint8_t state0 = 1;
uint8_t state1 = 1;
uint8_t state2 = 1;
uint8_t state3 = 1;
#define TEST_LENGTH_IN_BYTE    1*1024
#define MID_MEM_BASE           (1 * 512 * 1024 - TEST_LENGTH_IN_BYTE)
#define LAST_MEM_BASE          (2 * 1024 * 1024 - TEST_LENGTH_IN_BYTE)

uint32_t start_mem_data = 0x5a5a5a5a;
uint32_t mid_mem_data = 0xa3a3a3a3;
uint32_t last_mem_data = 0xf1f1f1f1;
uint32_t dataBuffer1[TEST_LENGTH_IN_BYTE/4];
uint32_t dataBuffer2[TEST_LENGTH_IN_BYTE/4];
uint32_t dataBuffer3[TEST_LENGTH_IN_BYTE/4];

void iomux_config(void)
{
    iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_ADDR_0_IOF_OVAL, 59, GMC0_GMC_ADDR_0_HS_SEL, 0, 0);
    iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_ADDR_1_IOF_OVAL, 60, GMC0_GMC_ADDR_1_HS_SEL, 0, 0);
    iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_ADDR_2_IOF_OVAL, 61, GMC0_GMC_ADDR_2_HS_SEL, 0, 0);
    iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_ADDR_3_IOF_OVAL, 62, GMC0_GMC_ADDR_3_HS_SEL, 0, 0);
    iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_ADDR_4_IOF_OVAL, 63, GMC0_GMC_ADDR_4_HS_SEL, 0, 0);
    iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_ADDR_5_IOF_OVAL, 64, GMC0_GMC_ADDR_5_HS_SEL, 0, 0);
    iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_ADDR_6_IOF_OVAL, 65, GMC0_GMC_ADDR_6_HS_SEL, 0, 0);
    iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_ADDR_7_IOF_OVAL, 66, GMC0_GMC_ADDR_7_HS_SEL, 0, 0);
    iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_ADDR_8_IOF_OVAL, 67, GMC0_GMC_ADDR_8_HS_SEL, 0, 0);
    iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_ADDR_9_IOF_OVAL, 68, GMC0_GMC_ADDR_9_HS_SEL, 0, 0);

    iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_ADDR_10_IOF_OVAL, 69, GMC0_GMC_ADDR_10_HS_SEL, 0, 0);
    iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_ADDR_11_IOF_OVAL, 70, GMC0_GMC_ADDR_11_HS_SEL, 0, 0);
    iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_ADDR_12_IOF_OVAL, 71, GMC0_GMC_ADDR_12_HS_SEL, 0, 0);
    iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_ADDR_13_IOF_OVAL, 72, GMC0_GMC_ADDR_13_HS_SEL, 0, 0);
    iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_ADDR_14_IOF_OVAL, 73, GMC0_GMC_ADDR_14_HS_SEL, 0, 0);
    iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_ADDR_15_IOF_OVAL, 74, GMC0_GMC_ADDR_15_HS_SEL, 0, 0);
    iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_ADDR_16_IOF_OVAL, 75, GMC0_GMC_ADDR_16_HS_SEL, 0, 0);
    iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_ADDR_17_IOF_OVAL, 76, GMC0_GMC_ADDR_17_HS_SEL, 0, 0);

    iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_ADDR_18_IOF_OVAL, 77, GMC0_GMC_ADDR_18_HS_SEL, 0, 0);
    // iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_ADDR_19_IOF_OVAL, 78, GMC0_GMC_ADDR_19_HS_SEL, 0, 0);
    // iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_ADDR_20_IOF_OVAL, 79, GMC0_GMC_ADDR_20_HS_SEL, 0, 0);
    // iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_ADDR_21_IOF_OVAL, 80, GMC0_GMC_ADDR_21_HS_SEL, 0, 0);
    // iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_ADDR_22_IOF_OVAL, 81, GMC0_GMC_ADDR_22_HS_SEL, 0, 0);
    // iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_ADDR_23_IOF_OVAL, 82, GMC0_GMC_ADDR_23_HS_SEL, 0, 0);
    // iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_ADDR_24_IOF_OVAL, 83, GMC0_GMC_ADDR_24_HS_SEL, 0, 0);
    // iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_ADDR_25_IOF_OVAL, 84, GMC0_GMC_ADDR_25_HS_SEL, 0, 0);

    iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_DQ_0_IOF_OVAL, 85, GMC0_GMC_DQ_0_HS_SEL, 0, 0);
    iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_DQ_1_IOF_OVAL, 86, GMC0_GMC_DQ_1_HS_SEL, 0, 0);
    iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_DQ_2_IOF_OVAL, 87, GMC0_GMC_DQ_2_HS_SEL, 0, 0);
    iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_DQ_3_IOF_OVAL, 88, GMC0_GMC_DQ_3_HS_SEL, 0, 0);
    iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_DQ_4_IOF_OVAL, 89, GMC0_GMC_DQ_4_HS_SEL, 0, 0);
    iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_DQ_5_IOF_OVAL, 90, GMC0_GMC_DQ_5_HS_SEL, 0, 0);
    iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_DQ_6_IOF_OVAL, 91, GMC0_GMC_DQ_6_HS_SEL, 0, 0);
    iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_DQ_7_IOF_OVAL, 92, GMC0_GMC_DQ_7_HS_SEL, 0, 0);

    iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_DQ_8_IOF_OVAL, 93, GMC0_GMC_DQ_8_HS_SEL, 0, 0);
    iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_DQ_9_IOF_OVAL, 94, GMC0_GMC_DQ_9_HS_SEL, 0, 0);
    iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_DQ_10_IOF_OVAL, 95, GMC0_GMC_DQ_10_HS_SEL, 0, 0);
    iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_DQ_11_IOF_OVAL, 96, GMC0_GMC_DQ_11_HS_SEL, 0, 0);
    iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_DQ_12_IOF_OVAL, 97, GMC0_GMC_DQ_12_HS_SEL, 0, 0);
    iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_DQ_13_IOF_OVAL, 98, GMC0_GMC_DQ_13_HS_SEL, 0, 0);
    iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_DQ_14_IOF_OVAL, 99, GMC0_GMC_DQ_14_HS_SEL, 0, 0);
    iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_DQ_15_IOF_OVAL, 100, GMC0_GMC_DQ_15_HS_SEL, 0, 0);

    // iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_DQ_16_IOF_OVAL, 101, GMC0_GMC_DQ_16_HS_SEL, 0, 0);
    // iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_DQ_17_IOF_OVAL, 0, GMC0_GMC_DQ_17_HS_SEL, 0, 0);
    // iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_DQ_18_IOF_OVAL, 1, GMC0_GMC_DQ_18_HS_SEL, 0, 0);
    // iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_DQ_19_IOF_OVAL, 2, GMC0_GMC_DQ_19_HS_SEL, 0, 0);
    // iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_DQ_20_IOF_OVAL, 3, GMC0_GMC_DQ_20_HS_SEL, 0, 0);
    // iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_DQ_21_IOF_OVAL, 4, GMC0_GMC_DQ_21_HS_SEL, 0, 0);
    // iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_DQ_22_IOF_OVAL, 5, GMC0_GMC_DQ_22_HS_SEL, 0, 0);
    // iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_DQ_23_IOF_OVAL, 6, GMC0_GMC_DQ_23_HS_SEL, 0, 0);

    // iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_DQ_24_IOF_OVAL, 7, GMC0_GMC_DQ_24_HS_SEL, 0, 0);
    // iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_DQ_25_IOF_OVAL, 8, GMC0_GMC_DQ_25_HS_SEL, 0, 0);
    // iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_DQ_26_IOF_OVAL, 9, GMC0_GMC_DQ_26_HS_SEL, 0, 0);
    // //iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_DQ_27_IOF_OVAL, 10, GMC0_GMC_DQ_27_HS_SEL, 0, 0);
    // iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_DQ_28_IOF_OVAL, 11, GMC0_GMC_DQ_28_HS_SEL, 0, 0);
    // //iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_DQ_29_IOF_OVAL, 12, GMC0_GMC_DQ_29_HS_SEL, 0, 0);
    // iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_DQ_30_IOF_OVAL, 13, GMC0_GMC_DQ_30_HS_SEL, 0, 0);
    // iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_GMC_DQ_31_IOF_OVAL, 14, GMC0_GMC_DQ_31_HS_SEL, 0, 0);

    iomux_ls_iof_ival_cfg(IOMUX_BASE,GMC0_GMC_DQ_0_IOF_IVAL, 85, GMC0_GMC_DQ_0_HS_SEL, 0, 0);
    iomux_ls_iof_ival_cfg(IOMUX_BASE,GMC0_GMC_DQ_1_IOF_IVAL, 86, GMC0_GMC_DQ_1_HS_SEL, 0, 0);
    iomux_ls_iof_ival_cfg(IOMUX_BASE,GMC0_GMC_DQ_2_IOF_IVAL, 87, GMC0_GMC_DQ_2_HS_SEL, 0, 0);
    iomux_ls_iof_ival_cfg(IOMUX_BASE,GMC0_GMC_DQ_3_IOF_IVAL, 88, GMC0_GMC_DQ_3_HS_SEL, 0, 0);
    iomux_ls_iof_ival_cfg(IOMUX_BASE,GMC0_GMC_DQ_4_IOF_IVAL, 89, GMC0_GMC_DQ_4_HS_SEL, 0, 0);
    iomux_ls_iof_ival_cfg(IOMUX_BASE,GMC0_GMC_DQ_5_IOF_IVAL, 90, GMC0_GMC_DQ_5_HS_SEL, 0, 0);
    iomux_ls_iof_ival_cfg(IOMUX_BASE,GMC0_GMC_DQ_6_IOF_IVAL, 91, GMC0_GMC_DQ_6_HS_SEL, 0, 0);
    iomux_ls_iof_ival_cfg(IOMUX_BASE,GMC0_GMC_DQ_7_IOF_IVAL, 92, GMC0_GMC_DQ_7_HS_SEL, 0, 0);

    iomux_ls_iof_ival_cfg(IOMUX_BASE,GMC0_GMC_DQ_8_IOF_IVAL, 93, GMC0_GMC_DQ_8_HS_SEL, 0, 0);
    iomux_ls_iof_ival_cfg(IOMUX_BASE,GMC0_GMC_DQ_9_IOF_IVAL, 94, GMC0_GMC_DQ_9_HS_SEL, 0, 0);
    iomux_ls_iof_ival_cfg(IOMUX_BASE,GMC0_GMC_DQ_10_IOF_IVAL, 95, GMC0_GMC_DQ_10_HS_SEL, 0, 0);
    iomux_ls_iof_ival_cfg(IOMUX_BASE,GMC0_GMC_DQ_11_IOF_IVAL, 96, GMC0_GMC_DQ_11_HS_SEL, 0, 0);
    iomux_ls_iof_ival_cfg(IOMUX_BASE,GMC0_GMC_DQ_12_IOF_IVAL, 97, GMC0_GMC_DQ_12_HS_SEL, 0, 0);
    iomux_ls_iof_ival_cfg(IOMUX_BASE,GMC0_GMC_DQ_13_IOF_IVAL, 99, GMC0_GMC_DQ_13_HS_SEL, 0, 0);
    iomux_ls_iof_ival_cfg(IOMUX_BASE,GMC0_GMC_DQ_14_IOF_IVAL, 100, GMC0_GMC_DQ_14_HS_SEL, 0, 0);
    iomux_ls_iof_ival_cfg(IOMUX_BASE,GMC0_GMC_DQ_15_IOF_IVAL, 101, GMC0_GMC_DQ_15_HS_SEL, 0, 0);

    // iomux_ls_iof_ival_cfg(IOMUX_BASE,GMC0_GMC_DQ_16_IOF_IVAL, 102, GMC0_GMC_DQ_16_HS_SEL, 0, 0);
    // iomux_ls_iof_ival_cfg(IOMUX_BASE,GMC0_GMC_DQ_17_IOF_IVAL, 32, GMC0_GMC_DQ_17_HS_SEL, 0, 0);
    // iomux_ls_iof_ival_cfg(IOMUX_BASE,GMC0_GMC_DQ_18_IOF_IVAL, 33, GMC0_GMC_DQ_18_HS_SEL, 0, 0);
    // iomux_ls_iof_ival_cfg(IOMUX_BASE,GMC0_GMC_DQ_19_IOF_IVAL, 34, GMC0_GMC_DQ_19_HS_SEL, 0, 0);  // also JTAG_TMS
    // iomux_ls_iof_ival_cfg(IOMUX_BASE,GMC0_GMC_DQ_20_IOF_IVAL, 35, GMC0_GMC_DQ_20_HS_SEL, 0, 0);  // also JTAG_TCK
    // iomux_ls_iof_ival_cfg(IOMUX_BASE,GMC0_GMC_DQ_21_IOF_IVAL, 36, GMC0_GMC_DQ_21_HS_SEL, 0, 0);  // also JTAG_TDO
    // iomux_ls_iof_ival_cfg(IOMUX_BASE,GMC0_GMC_DQ_22_IOF_IVAL, 37, GMC0_GMC_DQ_22_HS_SEL, 0, 0);
    // iomux_ls_iof_ival_cfg(IOMUX_BASE,GMC0_GMC_DQ_23_IOF_IVAL, 38, GMC0_GMC_DQ_23_HS_SEL, 0, 0);

    // iomux_ls_iof_ival_cfg(IOMUX_BASE,GMC0_GMC_DQ_24_IOF_IVAL, 39, GMC0_GMC_DQ_24_HS_SEL, 0, 0);
    // iomux_ls_iof_ival_cfg(IOMUX_BASE,GMC0_GMC_DQ_25_IOF_IVAL, 40, GMC0_GMC_DQ_25_HS_SEL, 0, 0);
    // iomux_ls_iof_ival_cfg(IOMUX_BASE,GMC0_GMC_DQ_26_IOF_IVAL, 41, GMC0_GMC_DQ_26_HS_SEL, 0, 0);
    // //iomux_ls_iof_ival_cfg(IOMUX_BASE,GMC0_GMC_DQ_27_IOF_IVAL, 42, GMC0_GMC_DQ_27_HS_SEL, 0, 0); // also UART_RX
    // iomux_ls_iof_ival_cfg(IOMUX_BASE,GMC0_GMC_DQ_28_IOF_IVAL, 43, GMC0_GMC_DQ_28_HS_SEL, 0, 0);   // also JTAG_TDI
    // //iomux_ls_iof_ival_cfg(IOMUX_BASE,GMC0_GMC_DQ_29_IOF_IVAL, 44, GMC0_GMC_DQ_29_HS_SEL, 0, 0); // also UART_TX
    // iomux_ls_iof_ival_cfg(IOMUX_BASE,GMC0_GMC_DQ_30_IOF_IVAL, 45, GMC0_GMC_DQ_30_HS_SEL, 0, 0);
    // iomux_ls_iof_ival_cfg(IOMUX_BASE,GMC0_GMC_DQ_31_IOF_IVAL, 46, GMC0_GMC_DQ_31_HS_SEL, 0, 0);

    iomux_ls_iof_pullup_cfg(IOMUX_BASE,PAD91,GMC0_GMC_DQ_0_HS_SEL, 0, 0);
    iomux_ls_iof_pullup_cfg(IOMUX_BASE,PAD90,GMC0_GMC_DQ_1_HS_SEL, 0, 0);
    iomux_ls_iof_pullup_cfg(IOMUX_BASE,PAD89,GMC0_GMC_DQ_2_HS_SEL, 0, 0);
    iomux_ls_iof_pullup_cfg(IOMUX_BASE,PAD88,GMC0_GMC_DQ_3_HS_SEL, 0, 0);
    iomux_ls_iof_pullup_cfg(IOMUX_BASE,PAD87,GMC0_GMC_DQ_4_HS_SEL, 0, 0);
    iomux_ls_iof_pullup_cfg(IOMUX_BASE,PAD86,GMC0_GMC_DQ_5_HS_SEL, 0, 0);
    iomux_ls_iof_pullup_cfg(IOMUX_BASE,PAD85,GMC0_GMC_DQ_6_HS_SEL, 0, 0);
    iomux_ls_iof_pullup_cfg(IOMUX_BASE,PAD84,GMC0_GMC_DQ_7_HS_SEL, 0, 0);

    iomux_ls_iof_pullup_cfg(IOMUX_BASE,PAD99,GMC0_GMC_DQ_8_HS_SEL, 0, 0);
    iomux_ls_iof_pullup_cfg(IOMUX_BASE,PAD98,GMC0_GMC_DQ_9_HS_SEL, 0, 0);
    iomux_ls_iof_pullup_cfg(IOMUX_BASE,PAD97,GMC0_GMC_DQ_10_HS_SEL, 0, 0);
    iomux_ls_iof_pullup_cfg(IOMUX_BASE,PAD96,GMC0_GMC_DQ_11_HS_SEL, 0, 0);
    iomux_ls_iof_pullup_cfg(IOMUX_BASE,PAD95,GMC0_GMC_DQ_12_HS_SEL, 0, 0);
    iomux_ls_iof_pullup_cfg(IOMUX_BASE,PAD94,GMC0_GMC_DQ_13_HS_SEL, 0, 0);
    iomux_ls_iof_pullup_cfg(IOMUX_BASE,PAD93,GMC0_GMC_DQ_14_HS_SEL, 0, 0);
    iomux_ls_iof_pullup_cfg(IOMUX_BASE,PAD92,GMC0_GMC_DQ_15_HS_SEL, 0, 0);

    // iomux_ls_iof_pullup_cfg(IOMUX_BASE,PAD146,GMC0_GMC_DQ_16_HS_SEL, 0, 0);
    // iomux_ls_iof_pullup_cfg(IOMUX_BASE,PAD145,GMC0_GMC_DQ_17_HS_SEL, 0, 0);
    // iomux_ls_iof_pullup_cfg(IOMUX_BASE,PAD144,GMC0_GMC_DQ_18_HS_SEL, 0, 0);
    // iomux_ls_iof_pullup_cfg(IOMUX_BASE,PAD143,GMC0_GMC_DQ_19_HS_SEL, 0, 0);  // also JTAG_TMS
    // iomux_ls_iof_pullup_cfg(IOMUX_BASE,PAD142,GMC0_GMC_DQ_20_HS_SEL, 0, 0);  // also JTAG_TCK
    // iomux_ls_iof_pullup_cfg(IOMUX_BASE,PAD141,GMC0_GMC_DQ_21_HS_SEL, 0, 0);  // also JTAG_TDO
    // iomux_ls_iof_pullup_cfg(IOMUX_BASE,PAD140,GMC0_GMC_DQ_22_HS_SEL, 0, 0);
    // iomux_ls_iof_pullup_cfg(IOMUX_BASE,PAD139,GMC0_GMC_DQ_23_HS_SEL, 0, 0);

    // iomux_ls_iof_pullup_cfg(IOMUX_BASE,PAD154,GMC0_GMC_DQ_24_HS_SEL, 0, 0);
    // iomux_ls_iof_pullup_cfg(IOMUX_BASE,PAD153,GMC0_GMC_DQ_25_HS_SEL, 0, 0);
    // iomux_ls_iof_pullup_cfg(IOMUX_BASE,PAD152,GMC0_GMC_DQ_26_HS_SEL, 0, 0);
    // //iomux_ls_iof_pullup_cfg(IOMUX_BASE,PAD151,GMC0_GMC_DQ_27_HS_SEL, 0, 0);  // also UART_RX
    // iomux_ls_iof_pullup_cfg(IOMUX_BASE,PAD150,GMC0_GMC_DQ_28_HS_SEL, 0, 0);    // also JTAG_TDI
    // //iomux_ls_iof_pullup_cfg(IOMUX_BASE,PAD149,GMC0_GMC_DQ_29_HS_SEL, 0, 0);  // also UART_TX
    // iomux_ls_iof_pullup_cfg(IOMUX_BASE,PAD148,GMC0_GMC_DQ_30_HS_SEL, 0, 0);
    // iomux_ls_iof_pullup_cfg(IOMUX_BASE,PAD147,GMC0_GMC_DQ_31_HS_SEL, 0, 0);

    /*sram/nor config*/
    // iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_O_GMC_NPC_CLK_IOF_OVAL, 46, GMC0_O_GMC_NPC_CLK_HS_SEL, 0, 0);
    // iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_O_GMC_NPC_NADV_IOF_OVAL, 46, GMC0_O_GMC_NPC_NADV_HS_SEL, 0, 0);
    iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_O_GMC_NPC_NBL_0_IOF_OVAL, 46, GMC0_O_GMC_NPC_NBL_0_HS_SEL, 0, 0);
    iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_O_GMC_NPC_NBL_1_IOF_OVAL, 46, GMC0_O_GMC_NPC_NBL_1_HS_SEL, 0, 0);
    // iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_O_GMC_NPC_NBL_2_IOF_OVAL, 46, GMC0_O_GMC_NPC_NBL_2_HS_SEL, 0, 0);
    // iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_O_GMC_NPC_NBL_3_IOF_OVAL, 46, GMC0_O_GMC_NPC_NBL_3_HS_SEL, 0, 0);
    iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_O_GMC_NPC_NE_0_IOF_OVAL, 46, GMC0_O_GMC_NPC_NE_0_HS_SEL, 0, 0);
    // iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_O_GMC_NPC_NE_1_IOF_OVAL, 46, GMC0_O_GMC_NPC_NE_1_HS_SEL, 0, 0);
    // iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_O_GMC_NPC_NE_2_IOF_OVAL, 46, GMC0_O_GMC_NPC_NE_2_HS_SEL, 0, 0);
    // iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_O_GMC_NPC_NE_3_IOF_OVAL, 46, GMC0_O_GMC_NPC_NE_3_HS_SEL, 0, 0);
    // iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_SDR_CS_N_0_IOF_OVAL, 46, GMC0_SDR_CS_N_0_HS_SEL, 0, 0);
    iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_O_GMC_NPC_NWE_IOF_OVAL, 46, GMC0_O_GMC_NPC_NWE_HS_SEL, 0, 0);
    iomux_ls_iof_oval_cfg(IOMUX_BASE,GMC0_O_GMC_NPC_NOE_IOF_OVAL, 46, GMC0_O_GMC_NPC_NOE_HS_SEL, 0, 0);

    // iomux_ls_iof_ival_cfg(IOMUX_BASE,GMC0_O_GMC_NPC_NWAIT_IOF_IVAL, 38, GMC0_O_GMC_NPC_NWAIT_HS_SEL, 0, 0);

    //PCRAM1_ZZ
    iomux_ls_iof_oval_cfg(IOMUX_BASE,LGPIO_IO_PORT_PINS_9_IOF_OVAL,56,LGPIO_IO_PORT_PINS_9_HS_SEL,0,0);
    LGPIO_Output_Enable(LGPIO,1<<9);
    LGPIO_WriteBit(LGPIO,1<<9,1);
    LGPIO_Mode(LGPIO,1<<9,PP);
    //CS_SW
    iomux_ls_iof_oval_cfg(IOMUX_BASE,LGPIO_IO_PORT_PINS_8_IOF_OVAL,59,LGPIO_IO_PORT_PINS_8_HS_SEL,0,0);
    LGPIO_Output_Enable(LGPIO,1<<8);
    LGPIO_WriteBit(LGPIO,1<<8,1);
    LGPIO_Mode(LGPIO,1<<8,PP);

}


void xec_iomux_cfg(void)
{
    iomux_ls_iof_oval_cfg(IOMUX_BASE, XEC_MDC_IOF_OVAL , 11, XEC_MDC_HS_SEL , 0 , 0);

    iomux_ls_iof_oval_cfg(IOMUX_BASE, XEC_MDIO_IOF_OVAL , 12, XEC_MDIO_HS_SEL , 0 , 0);
    iomux_ls_iof_ival_cfg(IOMUX_BASE, XEC_MDIO_IOF_IVAL , 12, XEC_MDIO_HS_SEL, 0, 0);
    //  iomux_ls_iof_inv_cfg(IOMUX_BASE, XEC_XMII_TXC_IOF_IVAL, XEC_XMII_TXC_HS_SEL ,0,0);
     
    iomux_iof_ival_cfg(IOMUX_BASE, XEC_XMII_TXC_IOF_IVAL , 0, XEC_XMII_TXC_HS_SEL ,0 , 0);
    // iomux_ls_iof_inv_cfg(IOMUX_BASE, XEC_GMII_RXC_IOF_OVAL, XEC_GMII_RXC_HS_SEL ,0,0);
    iomux_iof_ival_cfg(IOMUX_BASE, XEC_GMII_RXC_IOF_OVAL , 0, XEC_GMII_RXC_HS_SEL, 0,  0);
    iomux_iof_oval_cfg(IOMUX_BASE, XEC_GMII_TXEN_IOF_OVAL , 0, XEC_GMII_TXEN_HS_SEL , 0 , 0);
    iomux_iof_ival_cfg(IOMUX_BASE, XEC_GMII_RXDV_IOF_OVAL , 0, XEC_GMII_RXDV_HS_SEL, 0, 0);

    // iomux_iof_oval_cfg(IOMUX_BASE, XEC_GMII_TXER_IOF_OVAL , 0, XEC_GMII_TXER_HS_SEL, 0, 0);
    // iomux_iof_ival_cfg(IOMUX_BASE, XEC_GMII_RXER_IOF_IVAL , 0, XEC_GMII_RXER_HS_SEL, 0, 0);
    // iomux_iof_ival_cfg(IOMUX_BASE, XEC_GMII_CRS_IOF_IVAL , 0, XEC_GMII_CRS_HS_SEL, 0, 0);
    // iomux_iof_ival_cfg(IOMUX_BASE, XEC_GMII_COL_IOF_IVAL , 0, XEC_GMII_COL_HS_SEL, 0, 0);

     iomux_iof_oval_cfg(IOMUX_BASE, XEC_GMII_TXD_BIT0_IOF_OVAL ,0, XEC_GMII_TXD_BIT0_HS_SEL ,0 ,0);
    // iomux_ls_iof_slew_rate(IOMUX_BASE, XEC_GMII_TXD_BIT0_IOF_OVAL ,0, 0 ,0 ,0);
     iomux_iof_oval_cfg(IOMUX_BASE, XEC_GMII_TXD_BIT1_IOF_OVAL ,0, XEC_GMII_TXD_BIT1_HS_SEL ,0 ,0);
    // iomux_ls_iof_slew_rate(IOMUX_BASE, XEC_GMII_TXD_BIT1_IOF_OVAL ,0, 0 ,0 ,0);
     iomux_iof_oval_cfg(IOMUX_BASE, XEC_GMII_TXD_BIT2_IOF_OVAL ,0, XEC_GMII_TXD_BIT2_HS_SEL ,0 ,0);
    // iomux_ls_iof_slew_rate(IOMUX_BASE, XEC_GMII_TXD_BIT2_IOF_OVAL ,0, 0 ,0 ,0);
     iomux_iof_oval_cfg(IOMUX_BASE, XEC_GMII_TXD_BIT3_IOF_OVAL ,0, XEC_GMII_TXD_BIT3_HS_SEL ,0 ,0);
    // iomux_ls_iof_slew_rate(IOMUX_BASE, XEC_GMII_TXD_BIT3_IOF_OVAL ,0, 0 ,0 ,0);
    // iomux_iof_oval_cfg(IOMUX_BASE, XEC_GMII_TXD_BIT4_IOF_OVAL ,0, XEC_GMII_TXD_BIT4_HS_SEL ,0 ,0);
    // iomux_iof_oval_cfg(IOMUX_BASE, XEC_GMII_TXD_BIT5_IOF_OVAL ,0, XEC_GMII_TXD_BIT5_HS_SEL ,0 ,0);
    // iomux_iof_oval_cfg(IOMUX_BASE, XEC_GMII_TXD_BIT6_IOF_OVAL ,0, XEC_GMII_TXD_BIT6_HS_SEL ,0 ,0);
    // iomux_iof_oval_cfg(IOMUX_BASE, XEC_GMII_TXD_BIT7_IOF_OVAL ,0, XEC_GMII_TXD_BIT7_HS_SEL ,0 ,0);

    iomux_iof_ival_cfg(IOMUX_BASE, XEC_GMII_RXD_BIT0_IOF_OVAL ,0, XEC_GMII_RXD_BIT0_HS_SEL ,0 ,0);
    iomux_iof_ival_cfg(IOMUX_BASE, XEC_GMII_RXD_BIT1_IOF_OVAL ,0, XEC_GMII_RXD_BIT1_HS_SEL ,0 ,0);
    iomux_iof_ival_cfg(IOMUX_BASE, XEC_GMII_RXD_BIT2_IOF_OVAL ,0, XEC_GMII_RXD_BIT2_HS_SEL ,0 ,0);
    iomux_iof_ival_cfg(IOMUX_BASE, XEC_GMII_RXD_BIT3_IOF_OVAL ,0, XEC_GMII_RXD_BIT3_HS_SEL ,0 ,0);
    // iomux_iof_ival_cfg(IOMUX_BASE, XEC_GMII_RXD_BIT4_IOF_OVAL ,0, XEC_GMII_RXD_BIT4_HS_SEL ,0 ,0);
    // iomux_iof_ival_cfg(IOMUX_BASE, XEC_GMII_RXD_BIT5_IOF_OVAL ,0, XEC_GMII_RXD_BIT5_HS_SEL ,0 ,0);
    // iomux_iof_ival_cfg(IOMUX_BASE, XEC_GMII_RXD_BIT6_IOF_OVAL ,0, XEC_GMII_RXD_BIT6_HS_SEL ,0 ,0);
    // iomux_iof_ival_cfg(IOMUX_BASE, XEC_GMII_RXD_BIT7_IOF_OVAL ,0, XEC_GMII_RXD_BIT7_HS_SEL ,0 ,0);
    ////////////////////yhf
    // iomux_ls_iof_ival_cfg(IOMUX_BASE,LGPIO_IO_PORT_PINS_0_IOF_IVAL,39,LGPIO_IO_PORT_PINS_0_HS_SEL,0,0);
    // iomux_ls_iof_ival_cfg(IOMUX_BASE,LGPIO_IO_PORT_PINS_1_IOF_IVAL,40,LGPIO_IO_PORT_PINS_1_HS_SEL,0,0);
    // iomux_ls_iof_ival_cfg(IOMUX_BASE,LGPIO_IO_PORT_PINS_2_IOF_IVAL,35,LGPIO_IO_PORT_PINS_2_HS_SEL,0,0);
    // iomux_ls_iof_ival_cfg(IOMUX_BASE,LGPIO_IO_PORT_PINS_3_IOF_IVAL,36,LGPIO_IO_PORT_PINS_3_HS_SEL,0,0);
    // iomux_ls_iof_ival_cfg(IOMUX_BASE,LGPIO_IO_PORT_PINS_4_IOF_IVAL,37,LGPIO_IO_PORT_PINS_4_HS_SEL,0,0);
    // iomux_ls_iof_ival_cfg(IOMUX_BASE,LGPIO_IO_PORT_PINS_5_IOF_IVAL,38,LGPIO_IO_PORT_PINS_5_HS_SEL,0,0);
    // iomux_ls_iof_ival_cfg(IOMUX_BASE,LGPIO_IO_PORT_PINS_4_IOF_IVAL,33,LGPIO_IO_PORT_PINS_6_HS_SEL,0,0);
    // iomux_ls_iof_ival_cfg(IOMUX_BASE,LGPIO_IO_PORT_PINS_5_IOF_IVAL,34,LGPIO_IO_PORT_PINS_7_HS_SEL,0,0);
    // iomux_ls_iof_ival_cfg(IOMUX_BASE,LGPIO_IO_PORT_PINS_3_IOF_IVAL,0,LGPIO_IO_PORT_PINS_3_HS_SEL,0,0);
    // iomux_ls_iof_ival_cfg(IOMUX_BASE,LGPIO_IO_PORT_PINS_4_IOF_IVAL,1,LGPIO_IO_PORT_PINS_4_HS_SEL,0,0);
    // iomux_ls_iof_ival_cfg(IOMUX_BASE,LGPIO_IO_PORT_PINS_5_IOF_IVAL,2,LGPIO_IO_PORT_PINS_5_HS_SEL,0,0);
    // iomux_ls_iof_ival_cfg(IOMUX_BASE,LGPIO_IO_PORT_PINS_24_IOF_IVAL,158,LGPIO_IO_PORT_PINS_24_HS_SEL,0,0);   
    // iomux_ls_iof_ival_cfg(IOMUX_BASE,LGPIO_IO_PORT_PINS_25_IOF_IVAL,159,LGPIO_IO_PORT_PINS_25_HS_SEL,0,0);
    ////////////////////yhf
}



void WriteReadWordToSRAM(uint32_t val, uint32_t addr, uint32_t length)
{
    uint32_t i;
    uint32_t wr_data, rd_data;

    wr_data = val;
    
    for (i = 0; i < length; i += 4) {
        REG32(addr + i) = wr_data;
        rd_data = REG32(addr + i);
        if (wr_data != rd_data) {
            state2 = 0;
            printf("WThenFastR <<ERR A: %08x, w %08x, r %08x\r\n", addr + i, wr_data, rd_data);
            while(1);
        } else { 
            printf("WThenFastR <<SUC A: %08x, w %08x, r %08x\r\n", addr + i, wr_data, rd_data);
        }
    }
}

void ContinueWriteWordFastToReadCompareSRAM(uint32_t addr, uint32_t length)
{
    uint32_t i;
    uint32_t val;
    uint32_t w_dat = 0;


    for (i = 0; i < length; i += 4) {
        //w_dat = i/4 << 16;//i + (i << 16);
        w_dat = i/4;
        //REG32(addr + i) = w_dat;
        // REG32(addr + i+524288) = w_dat;
        val = REG32(addr + i);
        if(w_dat != val) {
            printf("Fast RW addr %08x match err, write: %08x, read : %08x\r\n", addr + i, w_dat, val);
            //while(1);
            state0 = 0;
        } else {
            printf("Fast RW addr %08x match, write: %08x, read : %08x\r\n", addr + i, w_dat, val);
        }
    }
}

void ContinueWriteWordThenToReadCompareSRAM(uint32_t addr, uint32_t length)
{
    uint32_t i;
    uint32_t val;

    for (i = 0; i < length; i += 4) {
        REG32(addr + i) = i;
    }

    for (i = 0; i < length; i += 4) {
        val = REG32(addr + i);
        if(i != val) {
            printf("WC then R2C addr %08x match err, write: %08x, read : %08x\r\n", addr + i, i, val);
            state1 = 0;
            while(1);
        } else {
            printf("WC then R2C addr %08x match, write: %08x, read : %08x\r\n", addr + i, i, val);
        }
    }
}

void gmc_sram_one_addr_swtich(uint32_t test_addr)
{
        uint32_t i, wr_data, rd_data;
        for(i = 0; i < 32; i++)
        {
            wr_data = (1 << i);
            REG32(test_addr) = wr_data;

            rd_data = REG32(test_addr);
            
            if(rd_data != wr_data) {
                printf("Err << 1, W: %08x, R: %08x \r\n", wr_data, rd_data);
                while(1);
                state3 = 0;
            }
        }
        for(i = 0; i < 32; i++)
        {
            wr_data = ~(1 << i);
            REG32(test_addr) = wr_data;

            rd_data = REG32(test_addr);
            
            if(wr_data != rd_data) {
                printf("Err << 0, W: %08x, R: %08x \r\n", wr_data, rd_data); 
                while(1);   
                state3 = 0;
            }
        }
}
/////////////////////////////////////////////////////GMC test
void USART0_IRQHandler(void)
{
    //USART_SendData(USART1, USART1_send_buffer[USART1_send_n++]);
    if (USART_GetITStatus(USART0, USART_STATUS_RXIP) == SET) {
        USART_SendData(USART0, USART_ReceiveData(USART0));
    }


    //USART_ITConfig(USART0, USART_IE_RX, DISABLE);

}
void USART3_IRQHandler(void)
{
    //USART_SendData(USART1, USART1_send_buffer[USART1_send_n++]);
    if (USART_GetITStatus(USART3, USART_STATUS_RXIP) == SET) {
        USART_SendData(USART3, USART_ReceiveData(USART3));
    }


    //USART_ITConfig(USART0, USART_IE_RX, DISABLE);

}
void USART7_IRQHandler(void)
{
    //USART_SendData(USART7, USART7_send_buffer[USART7_send_n++]);
    if (USART_GetITStatus(USART7, USART_STATUS_RXIP) == SET) {
        USART_SendData(USART7, USART_ReceiveData(USART7));
    }


    //USART_ITConfig(USART7, USART_IE_RX, DISABLE);

}

void usart0_config(void)
{
    __enable_irq();

    ECLIC_Register_IRQ(USART0_IRQn, ECLIC_NON_VECTOR_INTERRUPT,
                                    ECLIC_LEVEL_TRIGGER, 1, 1,
                                    USART0_IRQHandler);

    USART_InitTypeDef usart_init_t;
    usart_init_t.USART_BaudRate = 115200;
    usart_init_t.USART_WordLength = USART_WordLength_8b;
    usart_init_t.USART_StopBits = USART_STOP_BIT_1;
    usart_init_t.USART_TX_CTL = USART_TXCTRL_ENABLE;
    usart_init_t.USART_RX_CTL = USART_RXCTRL_ENABLE;
    usart_init_t.USART_Parity = USART_PARITY_DISABLE;
    usart_init_t.USART_HardwareFlowControl = USART_HardwareFlowControl_NONE;
    USART_Init(USART0, &usart_init_t);


    /*USART set watermark and config tx/rx IE*/
    USART_Set_RxWaterMark(USART0, 0);
    USART_ITConfig(USART0, USART_IE_RX, ENABLE);

    // USART_Set_TxWaterMark(USART0, 1);
    // USART_ITConfig(USART0, USART_IE_TX, ENABLE);
}
void usart7_config(void)
{

    __enable_irq();

    ECLIC_Register_IRQ(USART7_IRQn, ECLIC_NON_VECTOR_INTERRUPT,
                                    ECLIC_LEVEL_TRIGGER, 1, 1,
                                    USART7_IRQHandler);

    USART_InitTypeDef usart_init_t;
    USART_StructInit(&usart_init_t);
    usart_init_t.USART_BaudRate = 115200;
    usart_init_t.USART_WordLength = USART_WordLength_8b;
    usart_init_t.USART_StopBits = USART_STOP_BIT_1;
    usart_init_t.USART_TX_CTL = USART_TXCTRL_ENABLE;
    usart_init_t.USART_Parity = USART_PARITY_DISABLE;
    usart_init_t.USART_HardwareFlowControl = USART_HardwareFlowControl_NONE;
    USART_Init(USART7, &usart_init_t);


    /*USART set watermark and config tx/rx IE*/
    USART_Set_RxWaterMark(USART7, 0);
    USART_ITConfig(USART7, USART_IE_RX, ENABLE);

    // USART_Set_TxWaterMark(USART0, 1);
    // USART_ITConfig(USART0, USART_IE_TX, ENABLE);
}
void scfat_test(void)
{
    printf("=============This is a scFAT demo on PCRAM====================\r\n");
    res_pcram_a = f_mount(&fs_pcram,"1:",1);

    /* Formatting test */
    //res_pcram_a == FR_NO_FILESYSTEM
    if(1) //res_pcram_a == FR_NO_FILESYSTEM
    {
        printf("Formatting start...\r\n");
        res_pcram_a=f_mkfs("1:",1,0);

        printf("FatFs structure:\r\n");
//
//        if(disk_read(1, ReadBuffer, 0, 1) == RES_OK){
//            for(int i = 0; i < 1024; i++)
//                printf("%d  ", ReadBuffer[i]);
//            printf("=======\r\n");
//        }

        if(res_pcram_a == FR_OK)
        {
            printf("Formatting success!\r\n");

            res_pcram_a = f_mount(NULL,"1:",1);

            res_pcram_a = f_mount(&fs_pcram,"1:",1);
        }
        else
        {
            printf("Formatting failed!\r\n");

            while(1);
        }
    }
    else if(res_pcram_a!=FR_OK)
    {
        printf("File system mount failed!\r\n");

        while(1);
    }
    else
    {
      printf("File system mount success!\r\n");
    }
/*----------------------- Writting test -----------------------------*/
    /* Open file, if not exist then create it */
    printf("\r\nPcram Writting test started...\r\n");
    myLog("before write pcram");
    myLog("pcram open1");
    res_pcram_a = f_open(&fnew, "1:test.scv",FA_CREATE_ALWAYS | FA_WRITE );
    myLog("pcram open2");
    if ( res_pcram_a == FR_OK )
    {
    	myLog("pcram write1");
        set_repeatNum(RUDY_SET_WRITE, gong_hao_write_repeat_num);// add by rudy 2021-03-26
        res_pcram_a=f_write(&fnew,WriteBuffer,sizeof(WriteBuffer),&fnum);
        myLog("pcram write2");
        if(res_pcram_a==FR_OK)
        {
        	printf("Writting success, byte number is: %d\n",fnum);
            printf("The Writting data is:\r\n%s\r\n",WriteBuffer);
        }
        else
        {
        	printf("!!Writting failed:(%d)\n",res_pcram_a);
        }
        myLog("pcram close1");
        f_close(&fnew);
        myLog("pcram close2");
    }
    else
    {
        printf("result is %d !!Open/Create file failed.\r\n",res_pcram_a);
    }
    myLog("after write pcram");
    printf("\r\nPcram Writting test ended...\r\n");

    delay_1ms(DEFAULT_DELAY_CNT);

//
///*------------------- Reading test ------------------------------------*/
    printf("\r\nPcram Reading test started...\r\n");
    myLog("before read pcram");
    res_pcram_a = f_open(&fnew, "1:test.scv", FA_OPEN_EXISTING | FA_READ);
    if(res_pcram_a == FR_OK)
    {
    	set_repeatNum(RUDY_SET_READ, gong_hao_read_repeat_num);
		res_pcram_a = f_read(&fnew, ReadBuffer, sizeof(ReadBuffer), &fnum);
		if(res_pcram_a==FR_OK)
		{
			printf("Reading success, byte number is: %d\r\n",fnum);
			printf("The reading data is:\r\n%s\r\n", ReadBuffer);
		}
		else
		{
			printf("Reading failed:(%d)\n",res_pcram_a);
		}
    }
    else
    {
    	printf("rusult is %d !!Open file failed.\r\n",res_pcram_a);
    }
    f_close(&fnew);
    myLog("after read pcram");
    printf("\r\nPcram Reading test ended...\r\n");
}

void flash_test(void)
{
    printf("=============This is a scFAT demo on flash====================\r\n");
    res_flash = f_mount(&fs_flash,"0:",1);

    /* Formatting test */
    //res_pcram_a == FR_NO_FILESYSTEM
    if(1) //res_pcram_a == FR_NO_FILESYSTEM
    {
        printf("Formatting start...\r\n");
        res_flash=f_mkfs("0:",1,0);

        printf("FatFs structure:\r\n");

        if(res_flash == FR_OK)
	    {
            printf("Formatting success!\r\n");

            res_flash = f_mount(NULL,"0:",1);

            res_flash = f_mount(&fs_flash,"0:",1);
        }
        else
        {
            printf("Formatting failed!\r\n");

            while(1);
        }
    }
    else if(res_flash!=FR_OK)
    {
        printf("File system mount failed!\r\n");

        printf("Maybe pcram initialize failed!\r\n");

        while(1);
    }
    else
    {
      printf("File system mount success!\r\n");
    }

/*----------------------- Writting test -----------------------------*/
    /* Open file, if not exist then create it */
    printf("\r\nFlash Writting test started...\r\n");
    myLog("befoe write flash");
    myLog("flash open1");
    res_flash = f_open(&fnew, "0:test.scv",FA_CREATE_ALWAYS | FA_WRITE );
     myLog("flash open2");
    if ( res_flash == FR_OK )
    {
    	myLog("flash write1");
    	set_repeatNum(RUDY_SET_WRITE, gong_hao_write_repeat_num);
    	res_flash=f_write(&fnew,WriteBuffer,sizeof(WriteBuffer),&fnum);
    	myLog("flash write2");
    	if(res_flash==FR_OK)
        {
            printf("Writting success, byte number is: %d\n",fnum);
            printf("The Writting data is:\r\n%s\r\n",WriteBuffer);
        }
        else
        {
            printf("!!Writting failed:(%d)\n",res_pcram_a);
        }
        myLog("flash close1");
        f_close(&fnew);
        myLog("flash close2");
    }
    else
    {
        printf("!!Open/Create file failed.\r\n");
    }
     myLog("after write flash");
    printf("\r\nFlash Writting test ended...\r\n");


    delay_1ms(DEFAULT_DELAY_CNT);

//
///*------------------- Reading test ------------------------------------*/
    printf("\r\nFlash Reading test started...\r\n");
    myLog("befoe read flash");
    res_flash = f_open(&fnew, "0:test.scv", FA_OPEN_EXISTING | FA_READ);
    if(res_flash == FR_OK)
    {
    	set_repeatNum(RUDY_SET_READ, gong_hao_read_repeat_num);
		res_flash = f_read(&fnew, ReadBuffer, sizeof(ReadBuffer), &fnum);
		if(res_flash==FR_OK)
		{
			printf("Flash Reading success, byte number is: %d\r\n",fnum);
			printf("The reading data is:\r\n%s\r\n", ReadBuffer);
		}
		else
		{
			printf("Reading failed:(%d)\n",res_pcram_a);
		}
    }
    else
    {
    	printf("!!Open file failed.\r\n");
    }
    f_close(&fnew);
    myLog("after read flash");
    printf("\r\nFlash Reading test ended...\r\n");
}

LITE_OS_SEC_TEXT VOID rudy_task1_entry(void)
{
    uint32_t val = 0;
    uint32_t ADDR = 0;
    uint32_t num = 0;
    uint32_t i = 0;
    uint64_t gmc_sram_addr_base = 0;
    while (1)
    {
    	printf("task1_entry!\r\n");
        //wwdg_counter_update(WWDG0,127);
//        printf("task1 WWDG feed dog\r\n");
        printf("\r\n======XXXXXX Prj LiteOS Demos scfat XXXXXX======\r\n");
        // delay_1ms(1000);


//        /*----------------------------------------------------------------------------*/
//        gmc_sram_addr_base = BANK_SRAM_ADDR;
//        ContinueWriteWordFastToReadCompareSRAM(gmc_sram_addr_base, 16);
//        /*----------------------------------------------------------------------------*/

        ///////FatFS TEST
          Timer_CounterValueConfig(TIMER0,0);
          flash_test();//FLASH
          // exmc_pcram_init();
          // exmc_pcram_clear(0x10000);
          scfat_test();//pcram
          show_logs();

//        exmc_pcram_init();
//        pcram_wakeup(1);
//		 for (i = 0; i < 100; i += 4) {
//			 val=0x12345678+i;
//			 REG32(BANK_SRAM_ADDR + i) = 0x12345678+i;
//			 printf("Fast RW addr %08x , write: %08x\r\n", i,val);
//		 }
//         printf("\r\n");
//        for (i = 0; i < 100; i += 4) {
//            val=REG32(BANK_SRAM_ADDR + i);
//            printf("Fast RW addr %08x , read: %08x\r\n", i,val);
//        }
//        printf("EXMC_PCRAM_BufferRead;\r\n");
//        val=9;
//        ADDR=6;
//        EXMC_PCRAM_BufferRead(ReadBuffer,ADDR,val);
//        num=0;
//        for (i = ADDR; i < ADDR+val; i++) {
//            printf("Fast RW addr %08x , read: %02x\r\n", i,ReadBuffer[0+num]);
//            num++;
//        }
//        printf("EXMC_PCRAM_BufferWrite;\r\n");
//       EXMC_PCRAM_BufferWrite(WriteBuffer,ADDR,val);
//       for (i = 0; i < 100; i += 4) {
//           val=REG32(BANK_SRAM_ADDR + i);
//           printf("Fast RW addr %08x , read: %08x\r\n", i,val);
//       }
//        while(1);

       //////delay_1ms TEST
       //printf("delay_1ms(2000)_entry!\r\n");
       //delay_1ms(2000);
       //printf("delay_1ms(2000)_end!\r\n");

        ///////PCRAM TEST
        // Timer_CounterValueConfig(TIMER0,0);
        // printf("START:Timer_CounterRead(TIMER0) is %d\r\n",Timer_CounterRead(TIMER0));
        // LOS_TaskDelay(1000);
        // printf("LOS_TaskDelay(1000):Timer_CounterRead(TIMER0) is %d\r\n",Timer_CounterRead(TIMER0));
        // LOS_TaskDelay(2000);
        // printf("LOS_TaskDelay(2000):Timer_CounterRead(TIMER0) is %d\r\n",Timer_CounterRead(TIMER0));
        
//        SPI_PCRAM_BuffWrite(WriteBuffer, 0x00, 16);
//        printf("SPI_PCRAM_BuffWrite(WriteBuffer, 0x00, 16) finish!\r\n");
//        SPI_PCRAM_BuffRead(ReadBuffer, 0x00, 16);
//        printf("SPI_PCRAM_BuffRead(ReadBuffer, 0x00, 16) finish!\r\n");
//        printf("ReadBuffer is:\r\n");
//        for(i=0;i<16;i++)
//        {
//            printf("0x%X ",ReadBuffer[i]);
//        	//printf("%c",ReadBuffer[i]);
//        }
//        printf("\r\n");
//        printf("ReadBuffer is:\r\n");
//        for(i=0;i<16;i++)
//        {
//            //printf("0x%X ",ReadBuffer[i]);
//        	printf("%c",ReadBuffer[i]);
//        }
//        printf("\r\n");

        LOS_TaskDelay(20000);
    }
}

LITE_OS_SEC_TEXT VOID rudy_task2_entry(void)
{
    int task1_co = 1;
    while (1)
    {
    	printf("task2_entry!\r\n");
//        LGPIO_Toggle(LGPIO,1);
//        printf("task2 LGPIO %d\n", task1_co++);
        LOS_TaskDelay(10000);
    }
}


static int rudy_task_Creat()
{
    int ret = 0;
    UINT32 uwRet = LOS_OK;
    UINT32  handle;
    TSK_INIT_PARAM_S rudy_task_init_param[10];


    memset (&rudy_task_init_param[0], 0, sizeof (TSK_INIT_PARAM_S));
    rudy_task_init_param[0].uwArg = (unsigned int)NULL;
    rudy_task_init_param[0].usTaskPrio = 11;
    rudy_task_init_param[0].pcName =(char *) "Rudy_pc_name";
    rudy_task_init_param[0].pfnTaskEntry = (TSK_ENTRY_FUNC)rudy_task1_entry;
    rudy_task_init_param[0].uwStackSize = 0x200U;
    uwRet = LOS_TaskCreate(&handle, &rudy_task_init_param[0]);
    if(LOS_OK == uwRet){
        ret += uwRet;
    }

    memset (&rudy_task_init_param[1], 0, sizeof (TSK_INIT_PARAM_S));
    rudy_task_init_param[1].uwArg = (unsigned int)NULL;
    rudy_task_init_param[1].usTaskPrio = 12;
    rudy_task_init_param[1].pcName =(char *) "Rudy_pc_name_2";
    rudy_task_init_param[1].pfnTaskEntry = (TSK_ENTRY_FUNC)rudy_task2_entry;
    rudy_task_init_param[1].uwStackSize = 0x200U;
    uwRet = LOS_TaskCreate(&handle, &rudy_task_init_param[1]);
    if(LOS_OK == uwRet){
        ret += uwRet;
    }

//    memset (&rudy_task_init_param[2], 0, sizeof (TSK_INIT_PARAM_S));
//    rudy_task_init_param[2].uwArg = (unsigned int)NULL;
//    rudy_task_init_param[2].usTaskPrio = 3;
//    rudy_task_init_param[2].pcName =(char *) "Rudy_pc_name_3";
//    rudy_task_init_param[2].pfnTaskEntry = (TSK_ENTRY_FUNC)rudy_task3_entry;
//    rudy_task_init_param[2].uwStackSize = 0x200U;
//    uwRet = LOS_TaskCreate(&handle, &rudy_task_init_param[2]);
//    if(LOS_OK == uwRet){
//        ret += uwRet;
//    }
//
//    memset (&rudy_task_init_param[3], 0, sizeof (TSK_INIT_PARAM_S));
//    rudy_task_init_param[3].uwArg = (unsigned int)NULL;
//    rudy_task_init_param[3].usTaskPrio = 4;
//    rudy_task_init_param[3].pcName =(char *) "Rudy_pc_name_4";
//    rudy_task_init_param[3].pfnTaskEntry = (TSK_ENTRY_FUNC)rudy_task4_entry;
//    rudy_task_init_param[3].uwStackSize = 0x200U;
//    uwRet = LOS_TaskCreate(&handle, &rudy_task_init_param[3]);
//    if(LOS_OK == uwRet){
//        ret += uwRet;
//    }
//
//    memset (&rudy_task_init_param[4], 0, sizeof (TSK_INIT_PARAM_S));
//    rudy_task_init_param[4].uwArg = (unsigned int)NULL;
//    rudy_task_init_param[4].usTaskPrio = 5;
//    rudy_task_init_param[4].pcName =(char *) "Rudy_pc_name_5";
//    rudy_task_init_param[4].pfnTaskEntry = (TSK_ENTRY_FUNC)rudy_task5_entry;
//    rudy_task_init_param[4].uwStackSize = 0x200U;
//    uwRet = LOS_TaskCreate(&handle, &rudy_task_init_param[4]);
//    if(LOS_OK == uwRet){
//        ret += uwRet;
//    }

    return ret;
}
//////

#if 1
extern int link_main(void *args);

static int link_test()
{
    int ret = -1;
    UINT32 uwRet = LOS_OK;
    UINT32  handle;
    TSK_INIT_PARAM_S task_init_param;

    memset (&task_init_param, 0, sizeof (TSK_INIT_PARAM_S));
    task_init_param.uwArg = (unsigned int)NULL;
    task_init_param.usTaskPrio = 2;
    task_init_param.pcName =(char *) "link_main";
    task_init_param.pfnTaskEntry = (TSK_ENTRY_FUNC)link_main;
    task_init_param.uwStackSize = 0x1000;
    uwRet = LOS_TaskCreate(&handle, &task_init_param);
    if(LOS_OK == uwRet){
        ret = 0;
    }
    return ret;
}
#endif

extern void XEC_IRQHandler(void);


int main() {

    /* configure EVAL_COM0 */

    UINT32 uwRet = LOS_OK;
    UINT32 SysTimer_set_Value;
//    char test_s[12];

    if(OS_SYS_CLOCK==10000000UL)
    {
        SysTimer_Stop();
        SysTimer_set_Value=SysTimer_GetControlValue();
        SysTimer_set_Value=(SysTimer_set_Value|0x04);
        SysTimer_SetControlValue(SysTimer_set_Value);
        SysTimer_Start();
    }



    uwRet = LOS_KernelInit();
    if (uwRet != LOS_OK)
    {
        return LOS_NOK;
    }
    osal_install_liteos();
    //USART CONFIG
//    usart0_config();
//   usart7_config();

    
    printf("LiteOS %d\n", uwRet);
    printf("Ver. 2023-06-14\n");
	// xec_iomux_cfg();
    // #if (LOSCFG_PLATFORM_HWI == NO)
	// ECLIC_Register_IRQ(XEC_IRQn, ECLIC_NON_VECTOR_INTERRUPT,
    //                              ECLIC_LEVEL_TRIGGER, 1, 1,
    //                              XEC_IRQHandler);


    // __enable_irq();
    // printf("ECLIC_Register_IRQ in main FINISH\r\n");
    // #endif

//    spi_pcram_init();
//
    // link_test();  /////
//    init_log();

    LOS_TicklessDisable();
    // LOS_TicklessEnable();
//   rudy_task_Creat();
     LOS_Inspect_Entry();
    (void)LOS_Start();
    return 0;
}
